`timescale  1 ns/1 ps

module axi_uart_tb();

`include "../../../common_interface_sim/axi4/axi4_bfm.svh"
`include "../../../common_interface_sim/axi4/axi4_drive.svh"

axi4_bfm axi4_bfm_i();

axi4_drive  axi4_drive_h;

logic           interrupt;

initial
begin
    axi4_drive_h = new(axi4_bfm_i);
    @(posedge  axi4_bfm_i.s_aresetn);
    axi4_drive_h.init();
    axi4_drive_h.write_config();
    axi4_drive_h.read_config();
    #1us axi4_drive_h.write_dword('h0C, 32'h00000003);
    #1us axi4_drive_h.read_dword(32'h00000000);
    #1us axi4_drive_h.write_dword('h04, 32'h00000011);
    #1us axi4_drive_h.write_dword('h04, 32'h00000022);
    #1us axi4_drive_h.read_dword(32'h00000000);

    forever
    begin
        wait(interrupt == 1)
        axi4_drive_h.read_dword(32'h00000000);
    end
end

axi_uart     uartEx01 
(
  .s_axi_aclk       (    axi4_bfm_i.s_aclk               ),        // input wire s_axi_aclk
  .s_axi_aresetn    (    axi4_bfm_i.s_aresetn            ),  // input wire s_axi_aresetn
  .interrupt        (    interrupt                       ),          // output wire interrupt
  .s_axi_awaddr     (    axi4_bfm_i.s_axi_awaddr[3:0]    ),    // input wire [3 : 0] s_axi_awaddr
  .s_axi_awvalid    (    axi4_bfm_i.s_axi_awvalid        ),  // input wire s_axi_awvalid
  .s_axi_awready    (    axi4_bfm_i.s_axi_awready        ),  // output wire s_axi_awready
  .s_axi_wdata      (    axi4_bfm_i.s_axi_wdata          ),      // input wire [31 : 0] s_axi_wdata
  .s_axi_wstrb      (    axi4_bfm_i.s_axi_wstrb          ),      // input wire [3 : 0] s_axi_wstrb
  .s_axi_wvalid     (    axi4_bfm_i.s_axi_wvalid         ),    // input wire s_axi_wvalid
  .s_axi_wready     (    axi4_bfm_i.s_axi_wready         ),    // output wire s_axi_wready
  .s_axi_bresp      (    axi4_bfm_i.s_axi_bresp          ),      // output wire [1 : 0] s_axi_bresp
  .s_axi_bvalid     (    axi4_bfm_i.s_axi_bvalid         ),    // output wire s_axi_bvalid
  .s_axi_bready     (    axi4_bfm_i.s_axi_bready         ),    // input wire s_axi_bready
  .s_axi_araddr     (    axi4_bfm_i.s_axi_araddr[3:0]    ),    // input wire [3 : 0] s_axi_araddr
  .s_axi_arvalid    (    axi4_bfm_i.s_axi_arvalid        ),  // input wire s_axi_arvalid
  .s_axi_arready    (    axi4_bfm_i.s_axi_arready        ),  // output wire s_axi_arready
  .s_axi_rdata      (    axi4_bfm_i.s_axi_rdata          ),      // output wire [31 : 0] s_axi_rdata
  .s_axi_rresp      (    axi4_bfm_i.s_axi_rresp          ),      // output wire [1 : 0] s_axi_rresp
  .s_axi_rvalid     (    axi4_bfm_i.s_axi_rvalid         ),    // output wire s_axi_rvalid
  .s_axi_rready     (    axi4_bfm_i.s_axi_rready         ),    // input wire s_axi_rready
  .rx               (                                    ),                        // input wire rx
  .tx               (                                    )// output wire tx
);
endmodule
